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LTC2450-1 1 24501f features applications description easy-to-use, ultra-tiny 16-bit ? adc the ltc ? 2450-1 is a low power, ultra-tiny 16-bit analog- to-digital converter designed for space constrained ap- plications requiring 16-bit performance. the LTC2450-1 uses a single 2.7v to 5.5v supply, accepts a single-ended analog input voltage, and communicates through an spi interface. it includes an integrated oscillator that does not require any external components. the delta-sigma modulator converter core provides single-cycle settling time for multiplexed applications. the converter is avail- able in a 6-pin, 2mm 2mm dfn package. the LTC2450-1 implements a proprietary input sampling scheme that reduces the average input sampling current several orders of magnitude. the LTC2450-1 is capable of up to 60 conversions per second and, due to the very large oversampling ratio, has extremely relaxed antialiasing requirements. the converter uses its power supply voltage as the reference voltage and the single-ended, rail-to-rail input voltage range extends from gnd to v cc . following a conversion, the LTC2450-1 can automatically enter a sleep mode and reduce its power to less than 500na. at an output rate of 1hz, the LTC2450-1 consumes an average of less than 25w from a 2.7v supply. typical application gnd to v cc single-ended input range 60 conversions per second 0.02lsb rms noise 16-bits, no missing codes 0.5mv offset error 4lsb full-scale error single conversion settling time for multiplexed applications single cycle operation with auto shutdown 350a supply current 50na sleep current internal oscillatorno external components required single supply, 2.7v to 5.5v operation spi interface ultra-tiny, 2mm 2mm dfn package system monitoring environmental monitoring direct temperature measurements instrumentation industrial process control data acquisition embedded adc upgrades sense sck v in 3-wire spi interface sdo LTC2450-1 gnd 0.1 f 0.1 f 10 f 2.7 to 5.5v v cc close to chip 1k 24501 ta01 cs integral nonlinearity input voltage (v) 0 ?.0 inl (lsb) ?.0 ?.0 0 1.0 3.0 0.5 1.0 1.5 2.0 24501 g02 2.5 3.0 2.0 ?.5 ?.5 ?.5 0.5 2.5 1.5 v cc = v ref = 3v t a = ?5 c, 25 c, 90 c , lt, ltc and ltm are registered trademarks of linear technology corporation. easy drive is a trademark of linear technology corporation. all other trademarks are the property of their respective owners.
LTC2450-1 2 24501f pin configuration electrical characteristics absolute maximum ratings supply voltage (v cc ) ................................... ?0.3v to 6v analog input voltage (v in ) ............ ?0.3v to (v cc + 0.3v) digital input voltage ...................... ?0.3v to (v cc + 0.3v) digital output voltage ................... ?0.3v to (v cc + 0.3v) operating temperature range ltc2450c-1 ............................................. 0c to 70c ltc2450i-1 .......................................... ?40c to 85c storage temperature range ................... ?65c to 150c (notes 1, 2) parameter conditions min typ max units resolution (no missing codes) (note 3) o 16 bits integral nonlinearity (note 4) o 210 lsb offset error o 0.5 2 mv offset error drift 0.02 lsb/c gain error o 0.01 0.02 % of fs gain error drift 0.02 lsb/c transition noise 1.4 v rms top view cs/ld sdi v out v cc gnd dc package 6-lead (2mm 2mm) plastic dfn t jmax = 125c, ja = 85c/w exposed pad (pin7) is gnd, must be soldered to pcb 4 5 7 6 3 2 1 sck t o pc c c ppl ll p mp , pc c t a = 25c. (n 2) analog input symbol parameter conditions min typ max units v in ip vl r o 0v cc c in in smpl cpcc 0.35 pf i dcleak (v in ) in dc lk c v in = gnd (n 5) v in = v cc (n 5) o o 10 10 1 1 10 10 a a i conv ip smpl c (n 9) 50 a t o pc c c ppl ll p mp , pc c t a = 25c. lead free finish tape and reel part marking package description temperature range ltc2450cdc-1trmpbf ltc2450idc-1trmpbf ltc2450cdc-1trpbf ltc2450idc-1trpbf lctr lctr 6-l (2mm 2mm) plc dfn 6-l (2mm 2mm) plc dfn 0c 70c 40c 85c cl ltc mk p pc p mp . cl ltc mk m - l p. f m m l p mk, p//.l.cm/l/ f m m p l pc c, p//.l.cm/pl/ t mp ll pp c. order information
LTC2450-1 3 24501f note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all voltage values are with respect to gnd. v cc = 2.7v to 5.5v unless otherwise speci? ed. note 3: guaranteed by design, not subject to test. note 4: integral nonlinearity is de? ned as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. the deviation is measured from the center of the quantization band. guaranteed by design, test correlation and 3 point transfer curve measurement. digital inputs and digital outputs symbol parameter conditions min typ max units v cc supply voltage 2.7 5.5 v i cc supply current conversion sleep ? c ? s = gnd (note 6) ? c ? s = v cc (note 6) 350 0.05 600 0.5 a a the denotes the speci? cations which apply over the full operating temperature range,otherwise speci? cations are at t a = 25c. (note 2) power requirements symbol parameter conditions min typ max units v ih high level input voltage v cc C 0.3 v v il low level input voltage 0.3 v i in digital input current C10 10 a c in digital input capacitance 10 pf v oh high level output voltage i o = C800 a v cc C 0.5 v v ol low level output voltage i o = C1.6ma 0.4 v i oz hi-z output leakage current C10 10 a the denotes the speci? cations which apply over the full operating temperature range,otherwise speci? cations are at t a = 25c. timing characteristics the denotes the speci? cations which apply over the full operating temperature range,otherwise speci? cations are at t a = 25c. symbol parameter conditions min typ max units t conv conversion time 14 16.6 21 ms f sck sck frequency range 2 mhz t lsck sck low period 250 ns t hsck sck high period 250 ns t 1 ? c ? s falling edge to sdo low z (notes 7, 8) 0100ns t 2 ? c ? s rising edge to sdo high z (notes 7, 8) 0100ns t 3 ? c ? s falling edge to sck falling edge 100 ns t kq sck falling edge to sdo valid (note 7) 0100ns note 5: ? c ? s = v cc . a positive current is ? owing into the dut pin. note 6: sck = v cc or gnd. sdo is high impedance. note 7: see figure 3. note 8: see figure 4. note 9: input sampling current is the average input current drawn from the input sampling network while the LTC2450-1 is actively sampling the input.
LTC2450-1 4 24501f typical performance characteristics integral nonlinearity integral nonlinearity maximum inl vs temperature offset error vs temperature gain error vs temperature transition noise vs temperature transition noise vs output code conversion mode power supply current vs temperature temperature ( c) ?0 inl (lsb) 2.0 5.0 25 75 100 24501 g03 1.0 0.5 4.0 3.0 1.5 4.5 0 3.5 2.5 ?5 0 50 v cc = 5v v cc = 4.1v v cc = 3v temperature ( c) ?0 7 6 5 4 3 2 1 0 25 75 24501 g04 ?5 0 50 100 offset (lsb) v cc = 4.1v v cc = 2.7v v cc = 5.5v temperature ( c) ?0 ? gain error (lsb) 0 1 2 3 5 ?5 02550 24501 g05 75 100 4 v cc = 4.1v v cc = 2.7v v cc = 5.5v temperature ( c) ?0 transition noise rms ( v) 1.50 3.00 10 70 90 24501 g06 1.00 0.25 0.50 0.75 2.50 2.00 1.25 2.75 0 2.25 1.75 ?0 ?0 30 50 v cc = 5v v cc = 4.1v v cc = 3v output code (normalized to full scale) 0 transition noise rms ( v) 1.50 3.00 0.80 1.00 24501 g07 1.00 0.25 0.50 0.75 2.50 2.00 1.25 2.75 0 2.25 1.75 0.20 0.40 0.60 v cc = 5v v cc = 3v t a = 25 c input voltage (v) 0 ?.0 inl (lsb) ?.0 ?.0 0 1.0 3.0 1.5 2.5 3.5 24501 g01 4.5 0.5 1.0 2.0 3.0 4.0 5.0 2.0 ?.5 ?.5 ?.5 0.5 2.5 1.5 v cc = v ref = 5v t a = ?5 c, 25 c, 90 c input voltage (v) 0 ?.0 inl (lsb) ?.0 ?.0 0 1.0 3.0 0.5 1.0 1.5 2.0 24501 g02 2.5 3.0 2.0 ?.5 ?.5 ?.5 0.5 2.5 1.5 v cc = v ref = 3v t a = ?5 c, 25 c, 90 c temperature ( c) ?5 ?5 0 conversion current ( a) 200 500 ? 35 55 24501 g08 100 400 300 15 75 95 v cc = 5v v cc = 3v v cc = 4.1v
LTC2450-1 5 24501f sleep mode power supply current vs temperature typical performance characteristics temperature ( c) ?5 ?5 0 sleep mode current (na) 100 250 ? 35 55 24501 g09 50 200 150 15 75 95 v cc = 5v v cc = 3v v cc = 4.1v temperature ( c) ?5 19 20 22 15 55 24501 g11 18 17 ?5 ? 35 75 95 16 15 21 conversion time (ms) v cc = 5.5v, 4.1v, 2.7v temperature ( c) ?0 10 average supply power ( w) 100 1000 10000 ?5 0 25 50 24501 g12 75 100 60 hz output sample rate 10 hz output sample rate 1 hz output sample rate conversion period vs temperature average supply power vs temperature, v cc = 3v
LTC2450-1 6 24501f pin functions v cc (pin 1): positive supply voltage and converter refer- ence voltage. bypass to gnd (pin 3) with a 10f capacitor in parallel with a low series inductance 0.1f capacitor located as close to the part as possible. v in (pin 2): analog input voltage. gnd (pin 3): ground. connect to a ground plane through a low impedance connection. ? c ? s (pin 4): chip select (active low) digital input. a low on this pin enables the sdo digital output. a high on this pin places the sdo output pin in a high imped- ance state. sdo (pin 5): three-state serial data output. sdo is used for serial data output during the data output state and can be used to monitor the conversion status. sck (pin 6): serial clock input. sck synchronizes the serial data output. while digital data is available (the adc is not in convert state) and ? c ? s is low (adc is not in sleep state) a new data bit is produced at the sdo output pin following every falling edge applied to the sck pin. exposed pad (pin 7): ground. the exposed pad must be soldered to the same point as pin 3. functional block diagram spi interface 16 bit a/d converter internal oscillator ref + cs sdo sck gnd v in v cc v cc ref 24501 bd figure 1. functional block diagram
LTC2450-1 7 24501f converter operation converter operation cycle the LTC2450-1 is a low power, delta-sigma analog- to-digital converter with a simple 3-wire interface (see figure 1). its operation is composed of three successive states: convert, sleep and data output. the oper- ating cycle begins with the convert state, is followed by the sleep state, and ends with the data output state (see figure 2). the 3-wire interface consists of serial data output (sdo), serial clock input (sck), and the active low chip select input ( ? c ? s). the convert state duration is determined by the ltc2450- 1 conversion time (nominally 16.6 milliseconds). once started, this operation can not be aborted except by a low power supply condition (v cc < 2.1v) which generates an internal power-on reset signal. after the completion of a conversion, the LTC2450-1 enters the sleep state and remains there until both the chip select and clock inputs are low ( ? c ? s = sck = low). following this condition the adc transitions into the data output state. data output sleep convert power-on reset yes 24501 f02 16th falling edge of sck or cs = high? sck = low and cs = low? no yes no figure 2. LTC2450-1 state transition diagram applications information while in the sleep state, whenever the chip select in- put is pulled high ( ? c ? s = high), the LTC2450-1s power supply current is reduced to less than 500na. when the chip select input is pulled low ( ? c ? s = low), and sck is maintained at a high logic level, the LTC2450-1 will return to a normal power consumption level. during the sleep state, the result of the last conversion is held inde? nitely in a static register. upon entering the data output state, sdo outputs the most signi? cant bit (d15) of the conversion result. during this state, the adc shifts the conversion result serially through the sdo output pin under the control of the sck input pin. there is no latency in generating this data and the result corresponds to the last completed conversion. a new bit of data appears at the sdo pin following each falling edge detected at the sck input pin. the user can reliably latch this data on every rising edge of the external serial clock signal driving the sck pin (see figure 3). the data output state concludes in one of two different ways. first, the data output state operation is completed once all 16 data bits have been shifted out and the clock then goes low. this corresponds to the 16 th falling edge of sck. second, the data output state can be aborted at any time by a low-to-high transition on the ? c ? s input. following either one of these two actions, the LTC2450-1 will enter the convert state and initiate a new conver- sion cycle. power-up sequence when the power supply voltage v cc applied to the con- verter is below approximately 2.1v, the adc performs a power-on reset. this feature guarantees the integrity of the conversion result. when v cc rises above this critical threshold, the converter generates an internal power-on reset (por) signal for approximately 0.5ms. the por signal clears all internal registers. following the por signal, the LTC2450-1 starts a conversion cycle and follows the succession of states described in figure 2. the ? rst conversion result following por is accurate within the speci? cations of the device if the power supply voltage v cc is restored within the operating range (2.7v to 5.5v) before the end of the por time interval.
LTC2450-1 8 24501f applications information input voltage range the adc is capable of digitizing true rail-to-rail input sig- nals. ignoring offset and full-scale errors, the converter will theoretically output an all zero digital result when the input is at ground (a zero scale input) and an all one digital result when the input is at v cc (a full-scale input). in an under-range condition, for all input voltages less than the voltage corresponding to output code 0, the converter will generate the output code 0. in an over-range condition, for all input voltages greater than the voltage corresponding to output code 65535 the converter will generate the output code 65535. output data format the LTC2450-1 generates a 16-bit direct binary encoded result. it is provided, msb ? rst, as a 16-bit serial stream through the sdo output pin under the control of the sck input pin (see figure 3). during the data output operation the ? c ? s input pin must be pulled low ( ? c ? s = low). the data output process starts with the most signi? cant bit of the result being present at the sdo output pin (sdo = d15) once ? c ? s goes low. a new data bit appears at the sdo output pin following every falling edge detected at the sck input pin. the output data can be reliably latched by the user using the rising edge of sck. ease of use the LTC2450-1 data output has no latency, ? lter settling delay or redundant results associated with the conversion cycle. there is a one-to-one correspondence between the conversion and the output data. therefore, multiplexing multiple analog input voltages requires no special ac- tions. the LTC2450-1 includes a proprietary input sampling scheme that reduces the average input current several orders of magnitude as compared to traditional delta sigma architectures. this allows external ? lter networks to interface directly to the LTC2450-1. since the average input sampling current is 50na, an external rc lowpass ? lter using a 1k and 0.1f results in <1lsb error. reference voltage range the converter uses the power supply voltage (v cc ) as the positive reference voltage (see figure 1). thus, the refer- ence range is the same as the power supply range, which extends from 2.7v to 5.5v. the LTC2450-1s internal noise level is extremely low so the output peak-to-peak noise remains well below 1lsb for any reference voltage within this range. thus the converter resolution remains at 1lsb independent of the reference voltage. inl, offset, and full- scale errors vary with the reference voltage as indicated by the typical performance characteristics graphs. these error terms will decrease with an increase in the reference voltage (as the lsb size in v increases). d 15 lsb sdo sck d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 0 d 1 24501 f03 t 1 t 3 t kq t lsck t hsck t 2 cs msb figure 3. data output timing
LTC2450-1 9 24501f conversion status monitor for certain applications, the user may wish to monitor the LTC2450-1 conversion status. this can be achieved by holding sck high during the conversion cycle. in this condition, whenever the ? c ? s input pin is pulled low ( ? c ? s = low), the sdo output pin will provide an indication of the conversion status. sdo = high is an indication of a conversion cycle in progress while sdo = low is an indication of a completed conversion cycle. an example of such a sequence is shown in figure 4. conversion status monitoring, while possible, is not required for LTC2450-1 as its conversion time is ? xed and equal at approximately 16.6ms (21ms maximum). therefore, ex- ternal timing can be used to determine the completion of a conversion cycle. serial interface the LTC2450-1 transmits the conversion result and receives the start of conversion command through a synchronous 3-wire interface. this interface can be used during the convert and sleep states to assess the conversion status and during the data output state to read the conversion result, and to trigger a new conversion. applications information serial interface operation modes the following are a few of the more common interface operation examples. many more valid control and serial data output operation sequences can be constructed based upon the above description of the function of the three digital interface pins. the modes of operation can be summarized as follows: 1) the LTC2450-1 functions with sck idle high (commonly known as cpol = 1) or idle low (commonly known as cpol = 0). 2) after the 16th bit is read, the user can choose one of two ways to begin a new conversion. first, one can pull ? c ? s high ( ? c ? s = ). second, one can use a high-low transition on sck (sck = ) . 3) at any time during the data output state, pulling ? c ? s high ( ? c ? s = ) causes the part to leave the i/o state, abort the output and begin a new conversion. 4) when sck = high, it is possible to monitor the conver- sion status by pulling ? c ? s low and watching for sdo to go low. this feature is available only in the idle-high (cpol = 1) mode. sleep t 1 t 2 sdo sck = hi convert 24501 f04 cs figure 4. conversion status monitoring mode
LTC2450-1 10 24501f applications information serial clock idle-high (cpol = 1) examples in figure 5, following a conversion cycle the LTC2450-1 automatically enters the low power sleep mode. the user can monitor the conversion status at convenient intervals using ? c ? s and sdo. ? c ? s is pulled low while sck is high to test whether or not the chip is in the convert state. while in the convert state, sdo is high while ? c ? s is low. in the sleep state, sdo is low while ? c ? s is low. these tests are not required operational steps but may be useful for some applications. when the data is available, the user applies 16 clock cycles to transfer the result. the ? c ? s rising edge is then used to initiate a new conversion. the operation example of figure 6 is identical to that of figure 5, except the new conversion cycle is triggered by the falling edge of the serial clock (sck). a 17th clock pulse is used to trigger a new conversion cycle. serial clock idle-low (cpol = 0) examples in figure 7, following a conversion cycle the LTC2450-1 automatically enters the low power sleep state. the user determines data availability (and the end of conversion) based upon external timing. the user then pulls ? c ? s low ( ? c ? s = ) and uses 16 clock cycles to transfer the result. following the 16th rising edge of the clock, ? c ? s is pulled high ( ? c ? s = ), which triggers a new conversion. the timing diagram in figure 8 is identical to that of figure 7, except in this case a new conversion is triggered by sck. the 16th sck falling edge triggers a new conversion cycle and the ? c ? s signal is subsequently pulled high. d 15 clk 1 clk 2 clk 3 clk 4 clk 15 clk 16 d 14 d 13 d 12 d 2 d 1 d 0 sd0 sck convert convert sleep low i cc data output 24501 f05 cs figure 5. idle-high (cpol = 1) serial clock operation example. the rising edge of ? c ? s starts a new conversion d 15 d 14 d 13 d 12 d 2 d 1 d 0 sd0 clk 1 clk 2 clk 3 clk 4 clk 15 clk 16 clk 17 sck convert convert sleep low i cc data output 24501 f06 cs figure 6. idle-high (cpol = 1) clock operation example. a 17th clock pulse is used to trigger a new conversion cycle
LTC2450-1 11 24501f examples of aborting cycle using ? c ? s for some applications the user may wish to abort the i/o cycle and begin a new conversion. if the LTC2450-1 is in the data output state, a ? c ? s rising edge clears the remaining data bits from memory, aborts the output cycle and triggers a new conversion. figure 9 shows an example of aborting an i/o with idle-high (cpol = 1) and figure 10 shows an example of aborting an i/o with idle-low (cpol = 0). a new conversion cycle can be triggered using the ? c ? s signal without having to generate any serial clock pulses as shown in figure 11. if sck is maintained at a low logic level, after the end of a conversion cycle, a new conversion operation can be triggered by pulling ? c ? s low and then high. when ? c ? s is pulled low ( ? c ? s = low), sdo will output the most signi? cant bit (d15) of the result of the just completed conversion. while a low logic level is maintained at sck pin and ? c ? s is subsequently pulled high ( ? c ? s = high) the remaining 15 bits of the result (d14:d0) are discarded and a new conversion cycle starts. following the aborted i/o, additional clock pulses in the convert state are acceptable, but excessive signal tran- sitions on sck can potentially create noise on the adc during the conversion, and thus may negatively in? uence the conversion accuracy. applications information d 15 d 14 d 13 d 12 d 2 d 1 d 0 sd0 clk 1 clk 2 clk 3 clk 4 clk 15 clk 14 clk 16 sck convert convert sleep low i cc data output 24501 f08 cs figure 8. idle-low (cpol = 0) clock. the 16th sck falling edge triggers a new conversion d 15 d 14 d 13 d 12 d 2 d 1 d 0 clk 1 clk 2 clk 3 clk 4 clk 14 clk 15 clk 16 sck sd0 convert convert sleep low i cc data output 24501 f07 cs figure 7. idle-low (cpol = 0) clock. ? c ? s triggers a new conversion
LTC2450-1 12 24501f d 15 d 14 d 13 clk 1 clk 2 clk 4 clk 3 convert convert sleep low i cc data output 24501 f09 sd0 sck cs figure 9. idle-high (cpol = 1) clock and aborted i/o example applications information d 15 d 14 d 13 sd0 clk 1 clk 2 clk 3 sck convert convert sleep low i cc data output 24501 f10 cs figure 10. idle-low (cpol = 0) clock and aborted i/o example sck = low sd0 convert convert sleep low i cc data output 24501 f11 d 15 cs figure 11. idle-low (cpol = 0) clock and minimum data output length example
LTC2450-1 13 24501f applications information 24501 f12 d 15 d 14 d 13 d 12 d 2 d 1 d 0 sd0 clk 1 clk 2 clk 3 clk 4 clk 15 clk 16 clk 17 sck convert convert sleep data output cs = low figure 12. 2-wire, idle-high (cpol = 1) serial clock, operation example 24501 f13 d 15 d 14 d 13 d 12 d 2 d 1 d 0 sd0 cs = low clk 1 clk 2 clk 3 clk 14 clk 4 clk 15 clk 16 sck convert convert data output figure 13. 2-wire, idle-low (cpol = 0) serial clock operation example 2-wire operation the 2-wire operation modes, while reducing the number of required control signals, should be used only if the LTC2450-1 low power sleep capability is not required. in addition the option to abort serial data transfers is no longer available. hardwire ? c ? s to gnd for 2-wire operation. figure 12 shows a 2-wire operation sequence which uses an idle-high (cpol = 1) serial clock signal. the conversion status can be monitored at the sdo output. following a conversion cycle, the adc enters sleep state and the sdo output transitions from high to low. subsequently 16 clock pulses are applied to the sck input in order to serially shift the 16 bit result. finally, the 17th clock pulse is applied to the sck input in order to trigger a new conversion cycle. figure 13 shows a 2-wire operation sequence which uses an idle-low (cpol = 0) serial clock signal. the conversion status cannot be monitored at the sdo output. following a conversion cycle, the LTC2450-1 bypasses the sleep state and immediately enters the data output state. at this moment the sdo pin outputs the most signi? cant bit (d15) of the conversion result. the user must use external timing in order to determine the end of conversion and result availability. subsequently 16 clock pulses are applied to sck in order to serially shift the 16-bit result. the 16th clock falling edge triggers a new conversion cycle. preserving the converter accuracy the LTC2450-1 is designed to reduce as much as possible the conversion result sensitivity to device decoupling, pcb layout, antialiasing circuits, line and frequency perturbations. nevertheless, in order to preserve the very high accuracy capability of this part, some simple precautions are desirable.
LTC2450-1 14 24501f applications information digital signal levels the LTC2450-1s digital interface is easy to use. its digital inputs (sck and ? c ? s) accept standard cmos logic levels and the internal hysteresis receivers can tolerate edge rates as slow as 100s. however, some considerations are required to take advantage of the exceptional accuracy and low supply current of this converter. the digital output signal sdo is less of a concern because it is not active during the conversion cycle. while a digital input signal is in the range 0.5v to v cc C0.5v, the cmos input receiver may draw additional current from the power supply. due to the nature of cmos logic, a slow transition within this voltage range may cause an increase in the power supply current drawn by the converter, particularly in the low power operation mode within the sleep state. thus, for low power consumption it is highly desirable to provide relatively fast edges for the two digital input pins sck and ? c ? s, and to keep the digital input logic levels at v cc or gnd. at the same time, during the convert state, undershoot and/or overshoot of fast digital signals connected to the LTC2450-1 pins may affect the conversion result. under- shoot and overshoot can occur because of an impedance mismatch at the converter pin combined with very fast transition times. this problem becomes particularly dif? cult when shared control lines are used and multiple re? ec- tions may occur. the solution is to carefully terminate all transmission lines close to their characteristic impedance. parallel termination is seldom an acceptable option in low power systems so a series resistor between 27 and 56 placed near the driver may eliminate this problem. the actual resistor value depends upon the trace impedance and connection topology. an alternate solution is to reduce the edge rate of the control signals, keeping in mind the concerns regarding slow edges mentioned above. particular attention should be given to con? gurations in which a continuous clock signal is applied to sck pin dur- ing the convert state. while LTC2450-1 will ignore this signal from a logic point of view the signal edges may create unexpected errors depending upon the relation between its frequency and the internal oscillator frequency. in such a situation it is bene? cial to use edge rates of about 10ns and to limit potential undershoot to less than 0.3v below gnd and overshoot to less than 0.3v above v cc . noisy external circuitry can potentially impact the output under 2-wire operation. in particular, it is possible to get the LTC2450-1 into an unknown state if an sck pulse is missed or noise triggers an extra sck pulse. in this situ- ation, it is impossible to distinguish sdo = 1 (indicating conversion in progress) from valid 1 data bits. as such, cpol = 1 is recommended for the 2-wire mode. the user should look for sdo = 0 before reading data, and look for sdo = 1 after reading data. if sdo does not return a 0 within the maximum conversion time (or return a 1 after a full data read), generate 16 sck pulses to force a new conversion. driving v cc and gnd the v cc and gnd pins of the LTC2450-1 converter are directly connected to the positive and negative reference voltages, respectively. a simpli? ed equivalent circuit is shown in figure 14. the power supply current passing through the parasitic layout resistance associated with these common pins will modify the adc reference voltage and thus negatively affect the converter accuracy. it is thus important to keep the v cc and gnd lines quiet, and to connect these supplies through very low impedance traces. in relation to the v cc and gnd pins, the LTC2450-1 com- bines internal high frequency decoupling with damping figure 14. LTC2450-1 analog pins equivalent circuit v cc i leak r sw (typ) 15k c e (typ) 0.35pf internal switching freuency = 4 mh r sw (typ) 15k r sw (typ) 15k v in i leak i leak gnd i leak v cc v cc v cc 24501 f14
LTC2450-1 15 24501f applications information figure 15. LTC2450-1 input drive equivalent circuit c eq 0.35pf (typ) r sw 15k (typ) i leak i leak v cc r s c in v sig c par v cc i conv 24501 f15 v in + elements which reduce the adc performance sensitivity to pcb layout and external components. nevertheless, the very high accuracy of this converter is best preserved by careful low and high frequency power supply decoupling. a 0.1f, high quality, ceramic capacitor in parallel with a 10f ceramic capacitor should be connected between the v cc and gnd pins, as close as possible to the package. the 0.1f capacitor should be placed closest to the adc package. it is also desirable to avoid any via in the circuit path starting from the converter v cc pin, passing through these two decoupling capacitors and returning to the converter gnd pin. the area encompassed by this circuit path, as well as the path length, should be minimized. very low impedance ground and power planes and star connections at both v cc and gnd pins are preferable. the v cc pin should have two distinct connections: the ? rst to the decoupling capacitors described above and the second to the power supply voltage. the gnd pin should have three distinct connections: the ? rst to the decoupling capacitors described above, the second to the ground return for the input signal source and the third to the ground return for the power supply voltage source. driving v in the v in input drive requirements can be best analyzed using the equivalent circuit of figure 15. the input signal v sig is connected to the adc input pin v in through an equivalent source resistance r s . this resistor includes both the actual generator source resistance and any additional optional resistor connected to the v in pin. an optional input capacitor c in is also connected to the adc v in pin. this capacitor is placed in parallel with the adc input parasitic capacitance c par . depending upon the pcb layout c par has typical values between 2pf and 15pf. in addition, the equivalent circuit of figure 15 includes the converter equivalent internal resistor r sw and sampling capacitor c eq . there are some immediate trade-offs in r s and c in without needing a full circuit analysis. increasing r s and c in can give the following bene? ts: 1) due to the LTC2450-1s input sampling algorithm, the input current drawn by v in during the conversion cycle is 50na. a high r s ? c in attenuates the high frequency components of the input current, and r s values up to 1k result in <1lsb error. 2) the bandwidth from v sig is reduced at v in .this band- width reduction isolates the adc from high frequency signals, and as such provides simple antialiasing and input noise reduction. 3) noise generated by the adc is attenuated before it goes back to the signal source. 4) a large c in gives a better ac ground at v in , helping reduce re? ections back to the signal source. 5) increasing r s protects the adc by limiting the current during an outside-the-rails fault condition. r s can be easily sized such as to protect against even extreme fault conditions. there is a limit to how large r s ? c in should be for a given application. increasing r s beyond a given point increases the voltage drop across r s due to the input current, to the point that signi? cant measurement errors exist. ad- ditionally, for some applications, increasing the r s ? c in product too much may unacceptably attenuate the signal at frequencies of interest.
LTC2450-1 16 24501f applications information figure 16. measured inl vs input voltage, c in = 0.1f, v cc = 5v, t a = 25c for most applications, it is desirable to implement c in as a high quality 0.1f ceramic capacitor and r s 1k. this capacitor should be located as close as possible to the actual v in package pin. furthermore the area encompassed by this circuit path as well as the path length should be minimized. in the case of a 2-wire sensor which is not remotely grounded, it is desirable to split r s and place series resistors in the adc input line as well as in the sensor ground return line which should be tied to the adc gnd pin using a star connection topology. figure 16 shows the measured LTC2450-1 inl vs input voltage as a function of r s value with an input capacitor c in = 0.1f. in some cases, r s can be increased above these guide- lines. the input current is zero while the adc is either in sleep or i/o modes. thus, if the time constant of the input r-c circuit = r s ? c in is of the same order magnitude or longer than the time periods between actual conversions, then one can consider the input current to be reduced correspondingly. these considerations need to be balanced out by the input signal bandwidth. the 3db bandwidth ? 1/(2 ? r s ? c in ). finally, if the recommended choice for c in is unacceptable for the users speci? c application, an alternate strategy is to eliminate c in and minimize c par and r s . in practical terms, this con? guration corresponds to a low impedance sensor directly connected to the adc through minimum length traces. actual applications include current measurements through low value sense resistors, temperature measure- ments, low impedance voltage source monitoring and so on. the resultant inl vs v in is shown in figure 17. the measurements of figure 17 include a c par capacitor cor- responding to a minimum size layout pad and a minimum width input trace of about 1 inch length. input voltage (v) 0 inl(lsb) ? 0 4 3 5 24501 f16 ? ?2 ?6 12 4 8 12 16 r s = 10k r s = 1k r s = 0 figure 17. measured inl vs v in , c in = 0, v cc = 5v, t a = 25c input voltage (v) 0 inl (lsb) 8 6 4 2 0 ? ? ? ? 4 24501 f17 123 5 3.5 0.5 1.5 2.5 4.5 r s = 1k r s = 10k r s = 0
LTC2450-1 17 24501f applications information noise contribution of the external drive circuit would be v n = n i ? /2 ? f i . then, the total system noise level can be estimated as the square root of the sum of (v n 2 ) and the square of the LTC2450-1 noise ? oor (2 v 2 ). aliasing the LTC2450-1 signal acquisition circuit is a sampled data system and as such suffers from input signal alias- ing. as can be seen from figure 19, due to the very high over-sample ratios the high frequency input signal attenu- ation is reasonably good. nevertheless a continuous time antialiasing ? lter connected at the input will preserve the converter accuracy when the input signal includes undesirable high frequency components. the antialias- ing function can be accomplished using the r s and c in components shown in figure 15 sized such that = r s ? c in > 450ns. figure 18. input signal attenuation vs frequency (low frequencies) figure 19. input signal attenuation vs frequency input signal frequency (mhz) 0 input signal attenuation (db) ?0 0 10.0 12.5 15.0 24501 f19 ?0 ?0 ?0 ?00 2.5 5.0 7.5 signal bandwidth and noise equivalent input bandwidth the LTC2450-1 includes a sinc 1 type digital ? lter with the ? rst notch located at f 0 = 60hz. as such the 3db input signal bandwidth is 26.54hz. the calculated LTC2450-1 input signal attenuation with frequency at low frequencies is shown in figure 18. the LTC2450-1 input signal attenuation with frequency over a wide frequency range is shown in figure 19. the converter noise level is about 1.4v rms and can be modeled by a white noise source connected at the input of a noise free converter. for a simple system noise analysis the v in drive circuit can be modeled as a single pole equivalent circuit character- ized by a pole location f i and a noise spectral density n i . if the converter has an unlimited bandwidth or at least a bandwidth substantially larger than f i , then the total input signal frequency (hz) 0 input signal attenuatioin (db) ?0 ?0 0 480 24501 f18 ?0 ?0 ?5 ?5 ? ?5 ?5 ?0 120 60 240 180 360 420 540 300 600
LTC2450-1 18 24501f thermistor measurement typical application cs v cc LTC2450-1 5v gnd sck v in 100nf 10k thermistor 1k to 10k sdo 24501 ta02
LTC2450-1 19 24501f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description dc package 6-lead plastic dfn (2mm 2mm) (reference ltc dwg # 05-08-1703) 2.00 0.10 (4 sides) note: 1. drawing to be made a jedec package outline m0-229 variation of (wccd-2) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.38 0.05 bottom view?xposed pad 0.56 0.05 (2 sides) 0.75 0.05 r = 0.115 typ 1.37 0.05 (2 sides) 1 3 6 4 pin 1 bar top mark (see note 6) 0.200 ref 0.00 ?0.05 (dc6) dfn 1103 0.25 0.05 0.50 bsc 0.25 0.05 1.42 0.05 (2 sides) recommended solder pad pitch and dimensions 0.61 0.05 (2 sides) 1.15 0.05 0.675 0.05 2.50 0.05 package outline 0.50 bsc pin 1 chamfer of exposed pad
LTC2450-1 20 24501f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2007 lt 0607 ? printed in usa related parts typical applications LTC2450-1 100nf r s < 10k 24501 ta05 easy passive input LTC2450-1 100nf preconditioned sensor with voltage output 1k v+ gnd v out 24501 ta04 easy active input part number description comments lt ? 1236a-5 precision bandgap reference, 5v 0.05% maximum, 5ppm/ c drift lt1461 micropower series reference, 2.5v 0.04% maximum, 3ppm/ c drift ltc1860/ltc1861 12-bit, 5v, 1-/2-channel 250ksps sar adc in msop 850a at 250ksps, 2a at 1ksps, so-8 and msop packages ltc1860l/ltc1861l 12-bit, 3v, 1-/2-channel 150ksps sar adc 450a at 150ksps, 10a at 1ksps, so-8 and msop packages ltc1864/ltc1865 16-bit, 5v, 1-/2-channel 250ksps sar adc in msop 850a at 250ksps, 2a at 1ksps, so-8 and msop packages ltc1864l/ltc1865l 16-bit, 3v, 1-/2-channel 150ksps sar adc 450a at 150ksps, 10a at 1ksps, so-8 and msop packages ltc2440 24-bit no latency ? tm adc 200nv rms noise, 8khz output rate, 15ppm inl ltc2450 ultra tiny, easy to use 16-bit ? adc with automatic offset calibration and 30hz output rate pin compatible with the LTC2450-1 ltc2480 16-bit, differential input, no latency ? adc, with pga, temperature sensor, spi easy drive input current cancellation, 600nv rms noise, tiny 10-lead dfn package ltc2481 16-bit, differential input, no latency ? adc, with pga, temperature sensor, i 2 c easy drive input current cancellation, 600nv rms noise, tiny 10-lead dfn package ltc2482 16-bit, differential input, no latency ? adc, spi easy drive input current cancellation, 600nv rms noise, tiny 10-lead dfn package ltc2483 16-bit, differential input, no latency ? adc, i 2 c easy drive input current cancellation, 600nv rms noise, tiny 10-lead dfn package ltc2484 24-bit, differential input, no latency ? adc, spi easy drive input current cancellation, 600nv rms noise, tiny 10-lead dfn package ltc2485 24-bit, differential input, no latency ? adc, i 2 c easy drive input current cancellation, 600nv rms noise, tiny 10-lead dfn package ltc6241 dual, 18mhz, low noise, rail-to-rail op amp 550nv p-p noise, 125v offset maximum lt6660 micropower references in 2mm 2mm dfn package, 2.5v, 3v, 3.3v, 5v 20ppm/ c maximum drift, 0.2% maximum no latency ? is a trademark of linear technololgy corporation.

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